Method of Forming Solder Bump on High Topography Plated Cu

ABSTRACT

A solder bump is formed on a high-topography, electroplated copper pad integrating a first and second passivation layer. A sacrifice layer is deposited over the second passivation layer. The sacrifice layer is lithographically patterned. A via is etched in the sacrifice layer. A solder bump is formed in the via. A portion of the sacrifice layer is removed using the solder bump as a mask. A semiconductor device includes a substrate, an input/output (I/O) pad disposed over the substrate, a first passivation layer disposed over a portion of the I/O pad, a first conductive layer disposed over the first passivation layer, a second passivation layer disposed over the first conductive layer, a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via, and a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to an apparatus and method of forming a solder bump on high-topography electroplated copper (Cu) pads.

BACKGROUND OF THE INVENTION

Semiconductors, or computer chips, are found in virtually every electrical product manufactured today. Chips are used not only in very sophisticated industrial and commercial electronic equipment, but also in many household and consumer items such as televisions, clothes washers and dryers, radios, and telephones. As products become smaller but more functional, there is a need to include more chips in the smaller products to perform the functionality. The reduction in size of cellular telephones is one example of how more and more capabilities are incorporated into smaller and smaller electronic products.

Ball Grid Array (hereinafter referred to as BGA) packaging is widely applied to package the integrated circuits of chip sets or graphic chips, etc. Conventionally, the BGA packaging has tin balls provided on the bottom surface of a substrate and arranged in a form of an array. The balls serve as the leads or pins (conductive media) between a chip (or IC) and a circuit board, replacing the conventional lead frames. The BGA packaging can provide not only more pins but also more space between every two adjacent pins than that of conventional packaging, under the same size of substrate. In addition, BGA packaging provides superior heat dissipation and electrical conductivity by providing shorter conducting paths between the chip and the circuit board.

According to the raw material of the substrate, BGA substrates are divided into three categories: Plastic BGA (PBGA), Metal BGA (MBGA), and Tape BGA (TBGA). The PBGA substrate is made of organic materials such as compounds of BT resin and glass fiber. It is the most popular BGA substrate in the packaging industry.

To meet the need for shrinking package sizes and growing lead counts, flip chip and ball grid array (BGA) technologies have become increasingly popular. Flip chip relates to the attachment of an integrated circuit to a substrate while BGA relates to the attachment of a substrate to a printed circuit board or the like. Flip chip BGA packages (FCBGA), which combine the two technologies, are relatively small and have relatively high lead counts.

One conventional method of creating components of such wafer level package structures is shown in FIG. 1. A plurality of input/output 202 are disposed on a semiconductor substrate 201, and are used to transmit input or output signals. The input/output 202 are usually made of metal, such as gold (Au), aluminum (Al), or copper (Cu). The semiconductor substrate 201 and the input/output 202 are both covered by a passivation layer 203. The passivation layer 203 is usually made of oxide, (such as silicon dioxide (SiO.sub.2)), nitride (such as silicon nitride (Si.sub.3N.sub.4)), or other organic compounds (such as polyimide (PI)). The passivation layer 203 covers the semiconductor structure so as to protect circuits on the semiconductor structure 201.

A series of metal protection layers 204 a, 204 b, and 205 are used to protect the passivation layer 203 from damage. An under bump metallurgy layer (UBM layer) 206 is deposited on the protection layer 205. The under bump metallurgy layer 206 is usually made of copper (Cu), CuNi, gold (Au), or alloy, and is used as an adhesion layer for the metal solder bump 207. The metal solder bump 207 is located over the under bump metallurgy layer 206, and are usually made of conductive materials which can be used in electroplating technology, such as Sn/Pb alloy, copper (Cu), gold (Au), nickel (Ni), or indium (In).

In the manufacturing process involving high-topography, electroplated copper (Cu) pads, passivation material such as passivation layer 203 tends to crack. Hence, the prior art use of protection layers 204 a, 204 b, and 205 is implemented as a possible solution to protect the passivation layer 203. In addition, polyimide (PI)/copper (Cu) interfaces typically located at the bottom of a via are attacked during the solder bumping process. Such protective measures as found in the prior art, however, are expensive and involve extra manufacturing steps which create additional manufacturing time and complexity in the manufacturing process.

SUMMARY OF THE INVENTION

In light of the foregoing, a need exists for a manufacturing method involving solder bumping, where associated passivation material is protected, yet manufacturing costs, time and complexities are reduced.

In one embodiment, the present invention is a method of forming a solder bump on a high-topography, electroplated copper pad having a first and second passivation layer, comprising depositing a sacrifice layer over the second passivation layer, lithographically patterning the sacrifice layer, etching a via in the sacrifice layer, forming a solder bump in the via, and removing a portion of the sacrifice layer using the solder bump as a mask.

In another embodiment, the present invention is a method of forming a solder bump for a semiconductor device, comprising forming a sacrifice layer over a first surface of the device, lithographically patterning the sacrifice layer, etching a via in the sacrifice layer, forming a solder bump in the via, and removing a portion of the sacrifice layer to re-expose the first surface of the device.

In another embodiment, the present invention is a semiconductor device, comprising a substrate, an input/output (I/O) pad disposed over the substrate, a first passivation layer disposed over a portion of the I/O pad, a first conductive layer disposed over the first passivation layer, a second passivation layer disposed over the first conductive layer, a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via, and a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.

In still another embodiment, the present invention is a method of manufacturing a semiconductor device, comprising providing a substrate, providing an input/output (I/O) pad disposed over the substrate, providing a first passivation layer disposed over a portion of the I/O pad, providing a first conductive layer disposed over the first passivation layer, providing a second passivation layer disposed over the first conductive layer, providing a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via, and providing a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example prior art semiconductor device having a series of protective metal layers formed over a passivation layer to protect the passivation layer;

FIG. 2 illustrates an example semiconductor device;

FIG. 3A illustrates an example first step in a manufacturing process;

FIG. 3B illustrates an example second step in a manufacturing process;

FIG. 3C illustrates an example third step in a manufacturing process;

FIG. 3D illustrates an example fourth step in a manufacturing process; and

FIG. 3E illustrates an example fifth step in a manufacturing process.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

A flip-chip semiconductor package with a lead frame is a combination of the lead frame serving as a chip carrier and a flip-chip structure in which a semiconductor chip is mounted on the lead frame in a flip-chip manner. Such semiconductor packages include the lead frame having a plurality of leads, or having a plurality of leads and a die pad; at least one chip, which is mounted and electrically connected to the leads via a plurality of solder bumps formed on an active surface of the chip, or which is mounted on the die pad and electrically connected to the leads via a plurality of solder bumps formed on the active surface of the chip; and an encapsulation body for encapsulating the lead frame, the chip and the solder bumps. Flip chip packaging technology provides an advantage that the solder bumps are self-aligned and can be completely bonded to the leads in a single process, which thereby is relatively more time and labor-effective, unlike a conventional wiring method by which a plurality of bonding wires for the electrical connection between chip and leads need to be formed one by one.

Since the solder bumps are usually made of tin (Sn) 63/lead (Pb) 37 alloy, and the lead frame is made of a solderable metal such as copper, during a reflow process for soldering the solder bumps to the leads, the solder bumps under a particular high temperature melt and collapse to form eutectic, thus resulting in an intermetallic compound between the solder bumps and the leads, and which is customarily referred to as a wetting step.

Semiconductor structures having electroplated copper (Cu) pad structures can be incorporated into such flip chip semiconductor devices, or can be fabricated for other similar devices or to suit a particular application.

Electroplated copper (Cu) pad structures can be thicker than aluminum structures, generally above 5 microns in thickness. In some manufacturing processes, materials such as polyimide are disposed above the copper structures. As a next step in some manufacturing processes, dry film stripping techniques are then used. The dry film stripping process can include strong solvents, which tend to crack materials such as polyimide, particularly at the junction of the copper pad.

A semiconductor device incorporating high-topography electroplated copper (Cu) pad structures can be manufactured with a technique as follows which serves to protect the passivation surface during the solder bumping process. In addition, the polyimide/copper (Pi/Cu) interface located at the bottom portion of the via is protected from fluxing chemicals attacking the interface during a solder reflow manufacturing process.

Turing to FIG. 2, an example semiconductor device 300 having incorporated high-topography electroplated copper (Cu) pad structures is presented which can be manufactured using techniques according to the present invention. Device 300 includes a substrate 302. An input/output (I/O) pad 304 is disposed over the substrate to promote electrical connectivity to the substrate.

A first passivation layer 306 is disposed over a portion of the pad 304 and the remainder of the substrate 302 as shown. Electroplated copper (Cu) structures such as copper layer 309 are disposed over the first passivation layer, along with an adhesion layer 307 and an optional barrier layer 308, depending on the thickness of Cu layer 309. Layers 307, 308 and 309 can form a Cu runner structure. The Cu runner 307, 308, 309 conducts electrical current from the via to the pad 304. A second passivation layer 310 is disposed over the layer 309.

In accordance with the present invention, a portion of a sacrifice layer 312 is shown on opposing sides of a solder ball 314 which is formed in vias of device 300 as shown. The sacrifice layer 312 is used during the manufacturing process to protect the passivation material, such as polyimide, from damage. At a later stage in the manufacturing process, the sacrifice layer 312 can be removed to re-expose the passivation material. In one embodiment, the sacrifice layer 312 is removed after either dry film/flux stripping. In another embodiment, the sacrifice layer 312 is removed after the completion of a solder bumping process, with the solder bumps used as a hard mask. In either case, the passivation/copper junction at the bottom of each via is protected from flux solvents attacking the junction during a solder reflow process.

Turning to FIG. 3A, an example first step of manufacturing device 300 is shown according to the present invention. At the depicted stage shown in FIG. 3A, device 300 includes a Cu runner 309 (redistribution layer) which is deposited and patterned on a first passivation layer 306. Again, layer 306 is deposited on a substrate 302 for structural support, and incorporates an I/O pad 304 to provide electrical connectivity. A Cu runner structure, which can include an adhesion layer 307, an optional barrier layer 308, and a Cu layer 309 is deposited on the first passivation layer 306. Again, the barrier layer 308 is optional and depends upon the thickness of the CU layer 309.

The adhesion layer 307 can be made of titanium (Ti), titanium/tungsten (TiW), tantalum (Ta), chromium (Cr), or a metal with similar properties. The thickness of the adhesion layer 307 can vary between 200 Angstroms to 1500 Angstroms.

Barrier layer 308 can include nickel-vanadium (NiV), chromium-copper (CrCu), tantalum nitride (TaN), or a similar metal or metal alloy. The thickness of the barrier layer can range from 400 Angstroms to 4000 Angstroms.

Turning to FIG. 3B, an example second step of manufacturing device 300 is depicted. A second passivation layer 310 is deposited and patterned over a portion of the Cu runner 307, 308, 309 and a portion of the first passivation layer 306 as shown. Layer 310 can include polyimide, benzocyclobutene (BCB), lead oxide (PbO), or similar materials.

At the depicted stage shown in FIG. 3C, device 300 consists of the substrate layer 302, the I/O pad 304 formed over the substrate, the first passivation layer 306 formed over a portion of the pad 304 and substrate 302, copper runners having layers 307, 308, and 309 formed over the layer 306, a second passivation layer 310 formed over the structures 308, and a sacrifice layer 312 which is initially formed over a portion of the copper layers 307, 308, and 309 and second passivation layer 310.

Sacrifice layer 312 is deposited and patterned to protect the passivation surface 310 during the solder bumping process. As shown, sacrifice layer 312 covers and protects the passivation layer 310. The sacrifice layer 312 can include such materials as titanium (Ti), titanium-tungsten (TiW), tantalum (Ta), silicon nitride (Si₃N₄), silicon dioxide (SiO₂), a silicide, or similar materials.

As a next step, the sacrifice layer 312 is patterned with lithography. An opening is etched or otherwise formed in a portion of the layer 312 to expose a surface of the copper layers 308 and provide electrical connectivity. A pair of solder bumps 314 are then formed in the vias of device 300 as shown in FIG. 3B. During the solder bumping process, the layer 312 acts to protect the passivation material 310 from cracking.

A portion of the sacrifice layer 312 which resides outside the contact of the solder balls 314 and the layer 310 is then removed after either one of two processes. The portion of the sacrifice layer 312 can be removed after a dry film/flux stripping process. In addition, the portion of the sacrifice layer 312 can be removed after the completing of an entire solder bumping manufacturing process, using the solder bumps 314 as a hard mask. The sacrifice layer 312 can be removed using a dry etching or wet etching manufacturing process.

Following the removal process, the portion of the layer 312 between the solder balls 314 and the layer 310 remains, partly to provide structural support. The portion of the layer 312 which lays outside of the solder zone is removed. A next step of manufacturing can then be undertaken for a particular application.

The semiconductor manufacturing techniques previously described can be carried out with tools and materials which are known in the art, such as the use of patterning or etching equipment. Implementation of a manufacturing technique such as the example method described provides an inexpensive, yet effective method of preserving passivation material during the solder bumping process. In addition, the polyimide/copper (Pi/Cu) interface located at the bottom of the via is protected from fluxing chemicals attacking the surfaces during a solder reflow manufacturing process.

Semiconductor devices 300 serve to continue to advance semiconductor technology at reduced fabrication cost, while resulting in larger overall repeatable quality. Devices 300 eliminate the need to fabricate a series of protective metal layers to protect a passivation material during the solder bumping process. In addition, the need to form an UBM structure is alleviated. Both innovations significantly lower manufacturing cost, time, and complexity.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims. 

1. A method of forming a solder bump on a high-topography, electroplated copper pad integrated with a first and second passivation layer, comprising: depositing a sacrifice layer over the second passivation layer; lithographically patterning the sacrifice layer; etching a via in the sacrifice layer; forming a solder bump in the via; and removing a portion of the sacrifice layer using the solder bump as a mask.
 2. The method of claim 1, wherein removing the portion of the sacrifice layer is performed pursuant to a wet etching or a dry etching manufacturing process.
 3. The method of claim 1, wherein the via exposes a portion of a copper pad to provide electrical connectivity from the solder bump to the copper pad.
 4. The method of claim 3, wherein the copper pad is disposed over the first passivation layer, the first passivation layer incorporating an input/output (I/O) pad to provide electrical connectivity.
 5. The method of claim 4, wherein the I/O pad is formed over a substrate to provide structural support.
 6. A method of forming a solder bump for a semiconductor device, comprising: forming a sacrifice layer over a first surface of the device; lithographically patterning the sacrifice layer; etching a via in the sacrifice layer; forming a solder bump in the via; and removing a portion of the sacrifice layer to re-expose the first surface of the device.
 7. The method of claim 6, wherein removing a portion of the sacrifice layer is performed subsequent to a dry film/flux stripping manufacturing process.
 8. The method of claim 6, wherein removing a portion of the sacrifice layer is performed pursuant to a dry etching manufacturing process.
 9. The method of claim 6, wherein removing a portion of the sacrifice layer is performed pursuant to a wet etching manufacturing process.
 10. The method of claim 6, wherein the via exposes a portion of a copper layer to provide electrical connectivity from the solder bump to the copper layer.
 11. The method of claim 10, wherein the copper layer is disposed over a first passivation layer, the first passivation layer incorporating an input/output (I/O) pad to provide electrical connectivity.
 12. The method of claim 11, wherein the I/O pad is formed over a substrate to provide structural support.
 13. A semiconductor device, comprising: a substrate; an input/output (I/O) pad disposed over the substrate; a first passivation layer disposed over a portion of the I/O pad; a first conductive layer disposed over the first passivation layer; a second passivation layer disposed over the first conductive layer; a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via; and a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.
 14. The semiconductor device of claim 13, wherein the portion of the sacrifice layer is removed subsequent to a dry film/flux stripping manufacturing process.
 15. The semiconductor device of claim 13, wherein the portion of the sacrifice layer is removed pursuant to a dry etching manufacturing process.
 16. The semiconductor device of claim 13, wherein the portion of the sacrifice layer is removed pursuant to a wet etching manufacturing process.
 17. The semiconductor device of claim 13, wherein the sacrifice layer is deposited and patterned over the second passivation layer to protect the second passivation layer during a solder bumping process.
 18. A method of manufacturing a semiconductor device, comprising: providing a substrate; providing an input/output (I/O) pad disposed over the substrate; providing a first passivation layer disposed over a portion of the I/O pad; providing a first conductive layer disposed over the first passivation layer; providing a second passivation layer disposed over the first conductive layer; providing a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via; and providing a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer.
 19. The method of manufacture of claim 18, wherein the portion of the sacrifice layer is removed subsequent to a dry film/flux stripping manufacturing process.
 20. The method of manufacture of claim 18, wherein the portion of the sacrifice layer is removed pursuant to a dry etching manufacturing process.
 21. The method of manufacture of claim 18, wherein the portion of the sacrifice layer is removed pursuant to a wet etching manufacturing process.
 22. The method of manufacture of claim 18, wherein the sacrifice layer is deposited and patterned over the second passivation layer to protect the second passivation layer during a solder bumping process. 